The present invention relates to semiconductors, more specifically, to a method of reducing semiconductor MIM capacitor leakage through a reduced via density layout.
In semiconductor integrated circuits (ICs), a semiconductor capacitor may be implemented to provide a capacitive component within the design of a semiconductor integrated device. The applications for these capacitors can include mixed signal (analog/digital) devices, RF (radio frequency) devices, and even decoupling capacitors for the filtering of high frequency signals and improved noise immunization.
One type of semiconductor capacitor, is called the MIMcap (Metal-Insulator-Metal capacitor) and is commonly used in silicon based processes for its versatility and consistency in reproduction in semiconductor processing. FIG. 1 shows a MIMcap 100 of the related art. This type of thin film capacitor comprises of 3 parallel layers: a base metal plate layer 110, followed by a non-conductive dielectric layer 120, and finally a top metal plate layer 130. When integrated into a semiconductor circuit, this device is formed onto the substrate 140 base level.
Formation of a semiconductor capacitor typically entails the deposition, patterning, and etching of various layers and compounds onto a semiconductor substrate. Generally, the first parallel layer (base plate) is formed by deposition of a conductive layer over the substrate surface, which is usually silicon. Alternatively, the surface of the substrate may be highly doped in order to provide a conductive top layer forming the bottom plate of the capacitor. The resulting conductive surface would then be spun with photoresist, and etched to follow an appropriate pattern. Similarly, a non-conductive insulating layer is deposited and formed accordingly, and patterned such that the insulating layer covers at least a portion of the conductive bottom plate. Typical materials for the insulating dielectric layer include Silicon Oxide, and Silicon Nitride. Finally, a second conducting layer, or the top plate of the capacitor is formed in a similar manner and manages to complete the capacitor. Depending on the process and/or IC, the capacitor may be further subjected to another nonconductive deposition to isolate the capacitor, or for another parallel process of the IC.
In order to connect a semiconductor capacitor to other components on the IC, a conductive contact plate is needed. Referring to FIG. 2, contact plates are generally used to wire bond the capacitor to other components of the IC or to connect to different layers of the IC circuit while preventing direct contact and possible damage to the capacitor plates itself. A top contact 210 is used to connect to the capacitor top plate 220, while a bottom contact 250 is used to connect to the capacitor bottom plate 260. The top contact 210 and bottom contact 250 also possess large surfaces to aid in bonding and making necessary physical connections. The contact plates 210, 250 are deposited on top of the isolation layer 230, which covers and protects the internals of the capacitor. Connections from contact plates 210, 250 to the capacitor plates 220, 260 are made directly through multiple vias 240. Vias 240 are metallic based connectors that form between etched holes through the isolation layer 230 to allow for direct connection with the capacitor plates 220, 260.
The formation of the vias 240 are accomplished by spinning photoresist onto the isolation layer 230 which protects the capacitor, and exposing and developing the photoresist to result in a pattern of exposed holes. These exposed areas will be etched, a process that removes selected portions of the insulating layer right down to the capacitor plates 220. In the case of MIM capacitors, the etching process is typically a plasma based process. Once the surface of the capacitor plates 220 is reached by etching, the vias 240 can be deposited, typically through chemical vapor deposition (CVD), from which the metal contact layer 210 can now be placed in contact with the vias 240.
In order to maximize current flow between the capacitor plates 220, 260 and the contact plates 210, 250 manufacturers typically maximize the number of vias 240 between the capacitor plates 220, 260 and the contact plates 210, 250 according to the available surface area on the semiconductor and the foundry design guidelines for a semiconductor process. The greater the number of vias 240, the lower the resistance path is between the capacitor plates 220, 260 and contact plates 210, 250. Therefore, it is advantageous to always maximize the number of allowable vias 240.
A precise process method for via formation is required, otherwise defects in the MIMcap may result. If via holes are overetched, portions of the top capacitor plate 220 will be removed. This will result in a damaged top capacitor plate 220 and possibly cause charge leakage through the dielectric. In the case of plasma etching, charge carriers may in fact be diffused through the top capacitor plate into the dielectric while etching, resulting in current leakage. In essence, charge leakage will deter a capacitors ability to store charge and reduce its overall capacitance value. In circuits where the predictable behavior and values of capacitors are crucial, this is an important consideration.
Etch depths are also experimentally found to increase with Via density. That is for a given process, if the number of via holes are increased during etching, the etch depth for each via hole is also found to increase. This may result in overetching, and excess removal of the capacitor top plate beyond recommendation.
To prevent excess capacitor leakage current and charge loss, it is desirable to not overetch vias during MIMcap fabrication in order to ensure a reliable MIMcap with predictable operational capacitance.